The present invention relates to techniques for clock recovery comprising a digital phase-locked loop circuitry and a plurality of phase rotators.
Clock recovery is an important technique to be used on the receiving side of electronic units. It is generally applied on received high-speed serial data streams which are transmitted without any reference clock signal.
New I/O standards applying clock recovery, such as PCI express generation 3 and 4, impose stringent requirements on the clock recovery jitter tolerance specifications. In some approaches, the circuitry for recovering clock signals uses a digital tracking loop and a phase rotator. A phase offset to be set by the phase rotator is tuned by the digital tracking loop depending on a relative phase shift of the incoming data with respect to a basic clock signal, wherein the phase rotator applies the phase offset to the basic clock signal to latch the incoming data stream. The tracking loop can generally be implemented as second order digital control loop, hence having a proportional and integral path to track phase and frequency, respectively.
However, in some instances, a clock recovery unit requires processing time before a timing of an analyzed data sample of an incoming data stream has its effect on a phase rotation of the basic clock signal. In some instances, the latency of a clock recovery unit is about several clock cycles. This latency has a negative effect on the stability of the phase control loop, which manifests itself as jitter peaking in jitter tolerance measurements.
Document U.S. Pat. No. 8,138,840 B2 discloses a method for controlling jitter in a digital phase-locked loop. The digital phase-locked loop comprises an adjustable delay line configured to receive at least one of a reference clock signal and a feedback clock signal as an input and to output a dithered signal, a phase and frequency detector configured to compare the reference clock signal and the feedback clock signal, wherein at least one of the clock signals is the dithered signal, to determine phase and frequency differences between the clock signals, and a digitally controlled oscillator configured to receive early or late determinations from the phase and frequency detector to adjust an output in accordance therewith, wherein the dithered signal distributes a jitter response to enhance the overall operation of the digital phase-locked loop.
Document US 2008/0056426 A1 discloses a clock recovery method and apparatus providing the flexibility to choose between a low jitter mode and a low latency mode. This is achieved by switching between a retime mode and a resync mode, wherein data can be synchronized or retransmitted with simultaneously reduced latency and jitter.
Document U.S. Pat. No. 7,724,862 B2 discloses an adjustable phase-locked loop with an adjustable phase shift. The phase-locked loop comprises a voltage-controlled oscillator configured to generate multiple phase-shifted output signals, multiple phase detectors configured to determine phase differences between the phase-shifted output signals and a reference clock, and a weighting device configured to weight the phase differences and generate a control signal for the voltage-controlled oscillator. Thereby, the function of phase generation and phase rotation is combined in a single compact unit.
Document Reutemann, R. et al., “A 4.5 MW/GB/S 6.4 GB/S 22+1-LANE SOURCE SYNCHRONOUS RECEIVER CORE WITH OPTIONAL CLEANUP PLL IN 65 NM CMOS”, IEEE Journal of Solid-State Circuits, Volume: 45, Issue: 12, December 2010 discloses a low-power source-synchronous link receiver macro for data rates of 3.2-6.4 Gb/s. A pulsed clock recovery with programmable bandwidth is implemented to save power in the clock recovery. Time dithering is applied to the clock recovery to avoid notches in the jitter tolerance curve. The receiver clock path incorporates both a clean-up PLL and a polyphase filter for RX clock generation, one of which can be chosen to generate the receive clock.
Document Heesoo Song et al., “A 1.0-4.0-GB/S ALL-DIGITAL CDR WITH 1.0-PS PERIOD RESOLUTION DCO AND ADAPTIVE PROPORTIONAL GAIN CONTROL”, IEEE Journal of Solid-State Circuits, Volume: 46, Issue: 2, February 2011, discloses an all-digital recovery circuit for multigigabit/s operation. The proposed digitally controlled oscillator incorporating a supply-controlled ring oscillator with a digitally controlled resistor generates wide-frequency-range multiphase clocks with fine resolution. With an adaptive proportional gain controller, which continuously adjusts a proportional gain, the proposed digital recovery circuit recovers data with a low-jitter clock and tracks large-input jitter rapidly, resulting in enhanced jitter performance. A digital frequency acquisition loop with a proportional control greatly reduces acquisition time.